Digital Signal Processing Reference
In-Depth Information
Architecture and Instruction Set
of the C6x Processor
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Architecture and instruction set of the TMS320C6x processor
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Addressing modes
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Assembler directives
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Linear assembler
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Programming examples using C, assembly, and linear assembly code
3.1 INTRODUCTION
Texas Instruments introduced the first-generation TMS32010 DSP in 1982, the
TMS320C25 in 1986 [1], and the TMS320C50 in 1991. Several versions of each of
these processors—C1x, C2x, and C5x—are available with different features, such as
faster execution speed. These 16-bit processors are all fixed-point processors and
are code-compatible.
In a von Neumann architecture, program instructions and data are stored in a
single memory space. A processor with a von Neumann architecture can make a
read or a write to memory during each instruction cycle. Typical DSP applications
require several accesses to memory within one instruction cycle. The fixed-point
processors C1x, C2x, and C5x are based on a modified Harvard architecture
with separate memory spaces for data and instructions that allow concurrent
accesses.
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