Input and Output with the DSK - Digital Signal Processing and Applications with the C6713 and C6416 DSK - page 41

converted is determined by the specific ADC circuitry on the codec, which is 6 V
p-p with the onboard codec. After the captured signal is processed, the result needs
to be sent to the outside world. Along the output path in Figure 2.1 is a DAC, which
performs the reverse operation of the ADC. An output filter smooths out or recon-
structs the output signal. ADC, DAC, and all required filtering functions are per-
formed by the single-chip codec AIC23 on board the DSK.
The AIC23 is a stereo audio codec based on sigma-delta technology [1-5]. The
functional block diagram of the AIC23 codec is shown in Figure 2.3. It performs all
the functions required for ADC and DAC, lowpass filtering, oversampling, and so
on. The AIC23 codec contains specifications for data transfer of words with length
16, 20, 24, and 32 bits. A diagram of the AIC23 codec interfaced to the C6713 DSK
is shown in 6713 _ dsk _ schem.pdf , included with the CCS package.
Sigma-delta converters can achieve high resolution with high oversampling
ratios but with lower sampling rates. They belong to a category in which the sam-
pling rate can be much higher than the Nyquist rate. Sample rates of 8, 16, 24, 32,
44.1, 48, and 96 kHz are supported and can be readily set in the program.
A digital interpolation filter produces the oversampling. The quantization noise
power in such devices is independent of the sampling rate. A modulator is included
to shape the noise so that it is spread beyond the range of interest. The noise spec-
trum is distributed between 0 and F s /2, so that only a small amount of noise is within
the signal frequency band. Therefore, within the actual band of interest, the noise
power is considerably lower. A digital filter is also included to remove the out-of-
band noise.
A 12-MHz crystal supplies the clocking to the AIC23 codec (as well as to the
DSP and the USB interface). Using this 12-MHz master clock, with oversampling
rates of 250 F s and 272 F s , an exact audio sample rate of 48 kHz (12 MHz/250) and a
CD rate of 44.1 kHz (12 MHz/272) can be obtained. The sampling rate is set by the
codec's register SAMPLERATE.
The ADC converts an input signal into discrete output digital words in a 2's-
complement format that corresponds to the analog signal value. The DAC includes
an interpolation filter and a digital modulator. A decimation filter reduces the digital
data rate to the sampling rate. The DAC's output is first passed through an internal
lowpass reconstruction filter to produce an output analog signal. Low noise perfor-
mance for both ADC and DAC is achieved using oversampling techniques with
noise shaping provided by sigma-delta modulators.
Communication with the AIC23 codec for input and output uses two multi-
channel buffered serial ports McBSPs on the C6713. McBSP0 is used as a uni-
directional channel to send a 16-bit control word to the AIC23. McBSP1 is used as
a bidirectional channel to send and receive audio data.
Alternative I/O daughter cards can be used for input and output. Such cards can
plug into the DSK through the external peripheral interface 80-pin connector J3 on
the DSK board.