Digital Signal Processing Reference
In-Depth Information
if (poll) while(!MCBSP_rrdy(DSK6713_AIC23_DATAHANDLE));//receiveready?
AIC_data.uint=MCBSP_read(DSK6713_AIC23_DATAHANDLE); //read data
...
return(AIC_data.uint);
}
short input_left_sample() //input to left channel
{
if(poll) while(!MCBSP_rrdy(DSK6713_AIC23_DATAHANDLE));//receiveready?
AIC_data.uint=MCBSP_read(DSK6713_AIC23_DATAHANDLE);//read->left chan
return(AIC_data.channel[LEFT]);
//return left channel data
}
short input_right_sample() //input to right channel
...
FIGURE 1.14. ( Continued )
The function comm_intr() in an interrupt-driven program or comm_poll()
in a polling-based program calls the appropriate functions to initialize the DSK.
These two functions are located in the init/comm. file. When using an interrupt-
driven program, interrupt #11 (INT11) is configured and enabled (selected). The
nonmaskable interrupt bit must be enabled as well as the global interrupt enable
(GIE) bit. A different interrupt, such as INT12, can be selected readily by modify-
ing slightly the init/comm. file and the vector file that contains the branching address
to the corresponding ISR in the main C source program. INT11 is generated via the
serial port (McBSP).
The function input_sample() is used to input data and the function
output_sample() to output data. Most of the examples throughout the topic
utilize the AIC23 codec in a mono format, defaulting to the left channel to read or
write a 16-bit data. The example loop_stereo. c in Chapter 2 illustrates the stereo
capability of the codec to input 16-bit data into each (left and right) channel and
output a 16-bit data from each channel. Some adaptive filtering examples in Chapter
7 use both input channels to acquire two different 16-bit input data signals.
The code input = input_sample(); , casting input as a short, acquires
16-bit data through the left (default) channel. Similarly, output _ sample ((short) . . .);
outputs 16-bit data from the left (default) channel.
A polling-based program (non-interrupt-driven) continuously polls or tests
whether or not data are ready to be received or transmitted. This scheme is in
general less efficient than the interrupt scheme. For input, the content of the serial
port control register (SPCR) bit 1 [the second least significant bit (LSB)], as shown
in Figure B.8 (Appendix B), is continuously tested to determine when data are avail-
able to be received or read. For output, the content of SPCR bit 17 is tested (Figure
B.8) to determine when data are available to be transmitted. An input data value is
accessed through the data receive register of the McBSP. An output data value is
sent through the data transmit register of McBSP.
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