Code Optimization - Digital Signal Processing and Applications with the C6713 and C6416 DSK - page 303

TABLE 8.4 Number of Cycles with Different Optimization Schemes for Both
Fixed- and Floating-Point Implementations (Count = 200)

Number of Cycles

Optimization Scheme Fixed-Point Floating-Point

1. No optimization 2 + (16 ¥ 200) = 3202 2 + (18 ¥ 200) = 3602

2. With parallel instructions 1 + (8 ¥ 200) = 1601 1 + (10 ¥ 200) = 2001

3. Two sums per iteration 1 + (8 ¥ 100) = 801 1 + (10 ¥ 100) + 7 = 1008

4. With software pipelining 7 + (100) + 1 = 108 9 + (100) + 15 = 124

obtained for different array sizes, since the number of cycles in the prolog and epilog
stages remain the same.
Note that for a count of 1000, the fixed- and floating-point implementations with
software pipeling take:

+ (

) +=

Fixed
Floating

- point

point

: 7 count 2 1 508 cycles

+ (

) +=

- : 9 count 2 15 524 cycles

REFERENCES

1. TMS320C6000 Programmer's Guide , SPRU198G, Texas Instruments, Dallas, TX, 2002.

2. Guidelines for Software Development Efficiency on the TMS320C6000 VelociTI Archi-

tecture , SPRA434, Texas Instruments, Dallas, TX, 1998.

3. TMS320C6000 CPU and Instruction Set , SPRU189F, Texas Instruments, Dallas, TX, 2000.

4. TMS320C6000 Assembly Language Tools User's Guide , SPRU186K, Texas Instruments,

Dallas, TX, 2002.

5. TMS320C6000 Optimizing C Compiler User's Guide , SPRU187G, Texas Instruments,

Dallas, TX, 2000.