Code Optimization - Digital Signal Processing and Applications with the C6713 and C6416 DSK - page 295

FIGURE 8.12. Dependency graph for two sums of products per iteration.
A similar dependency graph for a floating-point implementation can be obtained
using LDDW , MPYSP , and ADDSP in lieu of LDW , MPY/MPYH , and ADD , respectively,
in Figure 8.12. Note that the single-precision instructions ADDSP and MPYSP both
take four cycles to complete (three delay slots each).
8.5.3 Scheduling Table
Table 8.1 shows a scheduling table drawn from the dependency graph.
1. LDW starts in cycle 1.
2. MPY and MPYH must start five cycles after the LDW s due to the four delay slots.
Therefore, MPY and MPYH start in cycle 6.
3. ADD must start two cycles after MPY/MPYH due to the one delay slot of
MPY/MPYH. Therefore, ADD starts in cycle 8.
4. B has five delay slots and starts in cycle 3, since branching occurs in cycle 9,
after the ADD instruction.
5. SUB instruction must start one cycle before the branch instruction, since the
loop count is decremented before branching occurs. Therefore, SUB starts in
cycle 2.