Digital Signal Processing Reference
In-Depth Information
;
twosumlasmfloat.sa
Sum of products.Separate accum of even/odd terms
;Using double-word load LDDW for floating-point implementation
loop: LDDW *aptr++, ai1:ai0 ;64-bit word ai0 and ai1
LDDW *bptr++, bi1:bi0 ;64-bit word bi0 and bi1
MPYSP ai0, bi0, prodl ;lower 32-bit product
MPYSP ai1, bi1, prodh ;higher 32-bit product
ADDSP prodl, suml, suml ;accum 32-bit even terms
ADDSP prodh, sumh, sumh ;accum 32-bit odd terms
SUB count, 1, count ;decrement count
[count] B loop ;branch to loopa
FIGURE 8.4.
Separate sum of products with LDDW using ASM code for floating-point
implementation (
twosumlasmfloat.sa
).
Example 8.4: Sum of Products with Double-Word Load for Floating-Point
Implementation Using Linear ASM Code (
twosumlasmfloat
)
Figure 8.4 shows the linear ASM code
twosumlasmfloat
.
sa
used to obtain two
separate sums of products for a floating-point implementation. The double-word
load instruction
LDDW
loads a 64-bit data value and stores it in a pair of registers.
Each single-precision multiply instruction
MPYSP
performs a 32
32 multiplication.
The sums of products of the lower and upper 32 bits are performed to yield a sum
of both even and odd terms as 32 bits.
¥
Example 8.5: Dot Product with No Parallel Instructions for Fixed-Point
Implementation Using ASM Code (
dotpnp
)
Figure 8.5 shows the ASM code
dotpnp.asm
for the dot product with no instruc-
tions in parallel for a fixed-point implementation. A fixed-point implementation can
;
dotpnp.asm
ASM Code, no parallel instructions, fixed-point
MVK .S1 200, A1 ;count into A1
ZERO .L1 A7 ;init A7 for accum
LOOP LDH .D1 *A4++,A2 ;A2=16-bit data pointed by A4
LDH .D1 *A8++,A3 ;A3=16-bit data pointed by A8
NOP 4 ;4 delay slots for LDH
MPY .M1 A2,A3,A6 ;product in A6
NOP ;1 delay slot for MPY
ADD .L1 A6,A7,A7 ;accum in A7
SUB .S1 A1,1,A1 ;decrement count
[A1] B .S2 LOOP ;branch to LOOP
NOP 5 ;5 delay slots for B
FIGURE 8.5.
ASM code with no parallel instructions for fixed-point implementation
(
dotpnp.asm
).
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