Architecture and Instruction Set of the C6x Processor - Digital Signal Processing and Applications with the C6713 and C6416 DSK - page 117

Seed Array

6 5 4 3 2 1 0987654321

FIGURE 3.26. Pseudorandom noise generation diagram using LFSR.

of the array, and the process is repeated. The output is a 32-bit value. Sam-
pling at 8 kHz, verify that the generated noise spectrum is flat until it rolls off
at about 3.8 kHz, which is the cutoff frequency of the antialiasing filter on the
codec.

REFERENCES

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New York, 1990.

2. R. Chassaing, Digital Signal Processing Laboratory Experiments Using C and the

TMS320C31 DSK , Wiley, New York, 1999.

3. R. Chassaing, Digital Signal Processing with C and the TMS320C30 , Wiley, New York,

1992.

4. R. Chassaing and P. Martin, Parallel processing with the TMS320C40, Proceedings of the

1995 ASEE Annual Conference , June 1995.

5. R. Chassaing and R. Ayers, Digital signal processing with the SHARC, Proceedings of

the 1996 ASEE Annual Conference , June 1996.

6. TMS320C6000 CPU and Instruction Set , SPRU189F, Texas Instruments, Dallas, TX, 2000.

7. TMS320C6000 Peripherals , SPRU190D, Texas Instruments, Dallas, TX, 2001.

8. TMS320C6000 Programmer's Guide , SPRU198G, Texas Instruments, Dallas, TX, 2002.