Architecture and Instruction Set of the C6x Processor - Digital Signal Processing and Applications with the C6713 and C6416 DSK - page 100

The x associated with the functional unit designates a cross-path.
3.20.3 Load/Store Constraints
The address register to be used must be on the same side as the .D unit. The fol-
lowing code segment is valid:
LDW .D1 *A1,A2
|| LDW .D2 *B1,B2
whereas the following is not valid:
LDW .D1 *A1,A2
|| LDW .D2 *A3,B2
Furthermore, loading and storing cannot be from the same register file. A load (or
store) using one register file in parallel with another load (or store) must use a dif-
ferent register file. For example, the following code segment is valid:
LDW .D1 *A0,B1
|| STW .D2 A1,*B2
The following is also valid:
LDW .D1 *A0,B1
|| LDW .D2 *B2,A1
However, the following is not valid:
LDW .D1 *A0,A1
|| STW .D2 A2,*B2
3.20.4 Pipelining Effects with More Than One EP within an FP
Table 3.3 shows a previous pipeline operation representing eight instructions in par-
allel within one FP. Table 3.6 shows the pipeline operation when there is more than
one EP within an FP.
Consider the operation of six FPs (FP1 through FP6) through the pipeline. FP1
contains three execute packets, and FP2, FP3,...,FP6 each contains one EP. In
cycles 2 through 5, FP2 through FP5, each FP starts its program fetch phase. When
the CPU detects that FP1 contains more than one EP, it forces the pipeline to stall
so that EP2 and EP3, within FP1, can each start its dispatching (DP) phase in cycles
6 and 7, respectively. Each instruction within an FP has a “p” bit to specify whether