Digital Signal Processing Reference
In-Depth Information
addressing mode instruction to load into A7 the content in memory whose
address is specified by A2. Then A2 is incremented to point at the next
higher memory address.
The instruction
LDW
loads a 32-bit word. Two paths using .D1 and .D2
allow for the loading of data from memory to registers A and B using the
instruction
LDW
. The double-word load floating-point instruction
LDDW
on
the C6713 can simultaneously load two 32-bit registers into side A and
two 32-bit registers into side B.
(b)
The instruction
;store A1
Æ
(A4) offset by 20
STW .D2 A1,*+A4[20]
stores the 32-bit word A1 in memory whose address is specified by A4
offset by 20 words (32 bits) or 80 bytes. The address register A4 is pre-
incremented with offset, but it is not modified (two plus signs are used if
A4 is to be modified).
3.
Branch/Move
. The following code segment illustrates branching and data
transfer:
;move 16 LSBs of x address
Æ
A4
Loop MVKL .S1 x,A4
;move 16 MSBs of x address
Æ
A4
MVKH .S1 x,A4
.
.
.
SUB .S1 A1,1,A1
;decrement A1
;branch to Loop if A1 # 0
[A1] B
.S2 Loop
;five no-operation instructions
NOP
5
;store A3 into (A7)
STW .D1 A3,*A7
The first instruction moves the lower 16 bits (LSBs) of address
x
into register
A4. The second instruction moves the higher 16 bits (MSBs) of address
x
into
A4, which now contains the full 32-bit address of
x
. One must use the instruc-
tions
MVKL/MVKH
in order to get a 32-bit constant into a register.
Register A1 is used as a loop counter. After it is decremented with the
SUB
instruction, it is tested for a conditional branch. Execution branches to the
label or address
Loop
if A1 is not zero. If A1
0, execution continues and
data in register A3 are stored in memory whose address is specified (pointed)
by A7.
=
3.9 ASSEMBLER DIRECTIVES
An assembler directive is a message for the assembler (not the compiler) and is not
an instruction. It is resolved during the assembling process and does not occupy
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