Architecture and Instruction Set of the C6x Processor - Digital Signal Processing and Applications with the C6713 and C6416 DSK - page 75

are particularly useful for applications requiring intensive computations. Family
members of the C6x include both fixed-point (e.g., C62x, C64x) and floating-point
(e.g., C67x) processors. Other DSp's are also available from companies such as
Motorola and Analog Devices [5].
Other architectures include the Super Scalar, which requires special hardware to
determine which instructions are executed in parallel. The burden is then on the
processor more than on the programmer, as in the VLIW architecture. It does not
necessarily execute the same group of instructions, and as a result, it is difficult to
time. Thus, it is rarely used in DSP.

3.2 TMS320C6x ARCHITECTURE

The TMS320C6713 onboard the DSK is a floating-point processor based on the
VLIW architecture [6-10]. Internal memory includes a two-level cache architecture
with 4 kB of level 1 program cache (L1P), 4 kB of level 1 data cache (L1D), and
256 kB of level 2 memory shared between program and data space. It has a glueless
(direct) interface to both synchronous memories (SDRAM and SBSRAM) and
asynchronous memories (SRAM and EPROM). Synchronous memory requires
clocking but provides a compromise between static SRAM and dynamic DRAM,
with SRAM being faster but more expensive than DRAM.
On-chip peripherals include two McBSPs, two timers, a host port interface (HPI),
and a 32-bit EMIF. It requires 3.3 V for I/O and 1.26 V for the core (internal). Inter-
nal buses include a 32-bit program address bus, a 256-bit program data bus to accom-
modate eight 32-bit instructions, two 32-bit data address buses, two 64-bit data buses,
and two 64-bit store data buses. With a 32-bit address bus, the total memory space
is 2 32 4 GB, including four external memory spaces: CE0, CE1, CE2, and CE3.

Figure 3.1 shows a functional block diagram of the C6713 processor included with
CCS.
Independent memory banks on the C6x allow for two memory accesses within
one instruction cycle. Two independent memory banks can be accessed using two
independent buses. Since internal memory is organized into memory banks, two
loads or two stores of instructions can be performed in parallel. No conflict results
if the data accessed are in different memory banks. Separate buses for program,
data, and direct memory access (DMA) allow the C6x to perform concurrent
program fetches, data read and write, and DMA operations. With data and instruc-
tions residing in separate memory spaces, concurrent memory accesses are possible.
The C6x has a byte-addressable memory space. Internal memory is organized as
separate program and data memory spaces, with two 32-bit internal ports (two 64-
bit ports with the C64x) to access internal memory.
The C6713 on the DSK includes 264 kB of internal memory, which starts at
0x00000000 , and 16 MB of external SDRAM, mapped through CE0 starting at
0x80000000 . The DSK also includes 512 kB of Flash memory (256 kB readily avail-
able to the user), mapped through CE1 starting at 0x90000000 . Figure 3.2 shows

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