DSP Instruction Set Simulation - Signal Processing Systems - page 950

Retargetable Simulation
Several retargetable simulation frameworks are publicly available from open source
projects and universities, others are offered by commercial software vendors.
SimpleScalar is a retargetable simulator based on interpretation [ 3 ] . New proces-
sors are described using DEF files, which contain a set of C macro definitions
and plain C code. A similar environment is offered by the commercial SimiCS
simulator [ 43 ] , but instead of plain C code a specialized device modeling language
(DLM) is offered. The Liberty Simulation Environment (LSE) [ 70 ] supports
very detailed event-based simulation. Hardware structures are described using the
Liberty Structural Specification Language (LSS) [ 69 ] . Another approach is taken
by the Unisim project , 1 it relies on the SystemC language and its tools [ 68 ] to
provide an execution environment for the simulation of processors [ 2 ] . The project
offers several components, such as memories, caches, buses, and even complete
processors, with well defined interfaces that can quickly be integrated with other
components.
The listed simulation environments offer very powerful support for implementing
efficient and accurate simulation tools. However, the focus of these systems is
targeted towards simulation only. For design space exploration of application-
specific processors, an efficient simulation engine alone is not enough. Processor
description languages usually support the automatic generation of all the tools
needed for DSE. A book by Mishra and Dutt [ 46 ] provides an excellent introduction
to this topic and covers most of the contemporary languages.
LISA by CoWare Inc. is one of the most successful processor description
languages. The system provides powerful tools to automatically derive an efficient
simulator based on compiled simulation [ 50 ] or interpretation from a processor
specification. Nohl et al. propose the JIT-CC approach to speed up the simulation of
LISA models [ 49 ] by caching information on previously decoded instructions. The
LISA simulators can also be enhanced with hybrid simulation so that irrelevant parts
of the program can be fast-forwarded using native execution [ 29 ] . Time-consuming
accurate simulation is performed only where required.
A similarly mature processor modeling environment is offered by Target Com-
piler Technologies. Based on the nML processor description language [ 27 ] , a
complete tool chain for the modeled processor can be derived [ 30 ] , including
the retargetable simulator CHECKERS. Both the LISA and nML languages have
successfully been used during the design of commercial processors in the digital
signal processing domain, e.g., the CoolFlux DSP [ 60 ] .
The EXPRESSION language [ 33 ] has been developed at the University of
California, Irvine . 2 Efficient simulators based on compiled simulation [ 57 , 58 ] and
interpretive simulation can be derived from EXPRESSION models. The interpreter
1 http://unisim.org/site/.
2 http://www.ics.uci.edu/ ∼ express/.