DSP Instruction Set Simulation - Signal Processing Systems - page 941

of a platform providing only weak guarantees will require a careful design of the
simulator which inevitably causes additional overhead, while the converse situation
will cause much less of a headache.

6 Hardware Supported Simulation

Although today's workstation computers provide tremendous performance, the
speed of an instruction set simulator may be slow and often unsatisfactory. It
is also likely that the simulation overhead for complex Systems-On-Chip (SoC)
and multi-core devices will further increase in the future, and thus widen the gap
between simulation time and the actual execution time on a real system. Even though
instruction set simulation inherently offers a high degree of parallelism, it cannot
be fully exploited due to communication and synchronization overhead. Dedicated
hardware provides a promising approach to overcome this difficulty by leveraging
fine-grained parallelism. This section is primarily focussed on simulation platforms
that use field programmable gate arrays (FPGAs) in order to connect the simulator
to external hardware, or to perform simulation tasks within the FPGA itself. Other
approaches that rely on custom ASIC designs [ 20 , 22 , 32 ] also show impressive
results, but appear to be less applicable than general solutions.

6.1 Interfacing Simulators with Hardware

In the simplest case, instruction set simulation is performed entirely in software
by a workstation computer, while other devices are realized using FPGAs or real
hardware as depicted in Fig. 8 . This approach is particularly suited to system

Fig. 8 External hardware can
interface with an instruction
set simulator in software by
driving the hardware clock
from within the simulator.
The transmission of I/O data
is effectively synchronized
and can be controlled entirely
in software