DSP Instruction Set Simulation - Signal Processing Systems - page 930

// load instructions and data into MEM array
PC = start_address ;
while (isRunning) {
instr = MEM[PC/4]; // fetch the next instruction
PC += 4; // increment PC by 4 bytes
opcode = decode(instr);

// extract the opcode

switch ( opcode ) {
...
case ADDI: // add-immediate instruction
C = instr & 0xFFFF;
Rs = (instr >> 21) & 0x1F;
Rt = (instr >> 16) & 0x1F;
sum = IntegerAdd(REG[Rs], C);
if (Rt != 0) REG[Rt] = sum;
break ;

...
case SW: // store word instruction
C = instr & 0xFFFF;
Rx = (instr >> 21) & 0x1F;
Ry = (instr >> 16) & 0x1F;
MEM[(REG[Ry]+C)/4] = REG[Rx];
break ;

...

}

}

Fig. 1 Structure of an ISA interpreter for the MIPS architecture

2.1 The Classic Interpreter

The interpreter has an array MEM which models the RAM memory of the architecture
being simulated, and it has a variable PC which models the program counter register
of that architecture. If the computer has a set of numbered registers, an array REG
can be used to model those registers. A small portion of possible C code for an
interpreter of the MIPS instruction set is shown in Fig. 1 . It uses an array REG to
mimic a register file, it has a variable which holds the current state of the condition
code register, and its MEM array holds an exact replica of what would be in the main
memory of the simulated computer.
Two of the simpler instructions have been picked for the example code; even so,
there are some hidden complexities. For example, overflow by the add-immediate
instruction must be detected and must be handled in the same way as the simulated
architecture. This tricky detail is assumed to be implemented by the IntegerAdd
function.
The interpreter code can exactly mimic the hardware resources of the computer
being simulated. If caches, or other components of the system, need to be simulated,
the interpreter code can be augmented in a straightforward manner. An important
point is that additional code to monitor execution performance can easily be
added too.