Dynamic Dataflow Graphs - Signal Processing Systems - page 895

Receiver side functionality is then modeled in the body graph starting with the
actors d1 and d2 , which represent dequantizers. The actor Sn (“synthesize”) then
reconstructs speech instances using corresponding blocks of AR coefficients and
error signals. The actor P1 (“play”) represents an output interface for playing or
storing the resulting speech instances.
The model order (number of AR coefficients) M , speech segment size N ,and
zero-padded speech segment length R are determined on a per-segment basis by the
selector actor in the subinit graph. Existing techniques, such as the Burg segment
size selection algorithm and AIC order selection criterion [ 32 ] can be used for this
purpose.
The model of Fig. 2 can be optimized to eliminate the zero padding overhead
(modeled by the parameter R ). This optimization can be performed by converting the
design to a parameterized cyclo-static dataflow (PCSDF) representation. In PCSDF,
the parameterized dataflow meta model is integrated with CSDF as the base model
instead of SDF.
For further details on this speech compression application and its representations
in PSDF and PCSDF, the semantics of parameterized dataflow and PSDF, and quasi-
static scheduling techniques for PSDF, see [ 6 ] .
Parameterized cyclo-static dataflow (PCSDF), the integration of parameterized
dataflow meta-modeling with cyclo-static dataflow, is explored further in [ 57 ] .
The exploration of different models of computation, including PSDF and PCSDF,
for the modeling of software defined radio systems is explored in [ 5 ] . In [ 36 ] ,
Kee et al. explore the application of PSDF techniques to field programmable
gate array implementation of the physical layer for 3GPP-Long Term Evolution
(LTE). The integration of concepts related to parameterized dataflow in language
extensions for embedded streaming systems is explored in [ 41 ] . General techniques
for analysis and verification of hierarchically reconfigurable dataflow graphs are
explored in [ 46 ] .

5 Enable-Invoke Dataflow

Enable-invoke dataflow (EIDF) is another DSP-oriented dynamic dataflow mod-
eling technique [ 51 ] . The utility of EIDF has been demonstrated in the context
of behavioral simulation, FPGA implementation, and prototyping of different
scheduling strategies [ 49 - 51 ] . This latter capability—prototyping of scheduling
strategies—is particularly important in analyzing and optimizing embedded soft-
ware. The importance and complexity of carefully analyzing scheduling strategies
are high even for the restricted SDF model, where scheduling decisions have a major
impact on most key implementation metrics [ 9 ] . The incorporation of dynamic
dataflow features makes the scheduling problem more critical since application
behaviors are less predictable, and more difficult to understand through analytical
methods.