Methods and Tools for Mapping Process Networks onto Multi-Processor Systems-On-Chip - Signal Processing Systems - page 870

For all the mentioned platforms, the main challenge is to provide an efficient
FIFO channel implementation that allows overlapping computation and communi-
cation in order to reduce the runtime overhead as much as possible. Aspects that
play an important role in this context are the size and location of channel buffers,
the efficient use of DMA controllers for data transfers between processors, and the
minimization of synchronization messages.

4.4 Performance Analysis

The DOL design flow is targeted towards the design of real-time multi-media
and signal processing applications. These systems must meet real-time constraints,
which means that not only the correctness and performance of a system are of major
concern but also the timeliness of the computed results. Typical questions in this
context are:

￿ What is the response time to certain events? Is this response time within the

required real-time limits?

￿ Can the system accept additional load and still meet the quality-of-service and

real-time constraints?

￿ Is a system schedulable, that is, are all real-time constraints met?

To be able to answer these questions, a suitable combination of system design and
performance analysis is required. To this end, it is essential that the architecture,
application, and runtime-environment of a system are amenable to formal analysis,
because simulation or measurements are not able to provide guarantees about timing
properties. On the other hand, performance analysis methods with a reasonable
scope and accuracy need to be employed such that effects occurring in the system
implementation can be faithfully modeled. For MPSoC applications, this includes
the modeling of heterogeneous resources and their sharing, the modeling of complex
timing behavior arising from variable execution demands and interference on shared
resources, or the modeling of different processing semantics.
Many approaches have been proposed to solve this problem, see [ 12 ] for
an overview. Frequently used approaches are time-triggered and synchronous
approaches, for instance. In purely time-triggered approaches, such as the time-
triggered architecture [ 39 ] or Giotto [ 28 ] , processing time of resources is allocated
to tasks in fixed time slots. This fixed allocation facilitates analysis, but dimension-
ing of the slots turns out to be difficult for varying workloads. For instance, using
the worst-case workload for setting the slot sizes might lead to over-dimensioned
systems. Purely synchronous approaches implemented in synchronous languages,
such as Esterel, Lustre, and Signal, rely on a global clock that divides the execution
of a system into a sequence of atomic processing steps [ 5 ] . While synchronous
approaches are successfully used for single-processor systems, applying them to
MPSoCs is difficult because MPSoCs are usually split up into different (asyn-
chronous) clock domains such that the synchronous assumption does not hold.