Methods and Tools for Mapping Process Networks onto Multi-Processor Systems-On-Chip - Signal Processing Systems - page 859

performance
metric

worst
case

best
case

real system measurement simulation WCET/BCET

analysis

probabilistic
analysis

Fig. 2 Scope of different performance analysis methods for MPSoC

successfully used in the context of KPN design flows. These methods differ in
accuracy, evaluation time, set-up effort, and scope.
In Fig. 2 , the scope of different performance analysis methods is compared.
Leftmost, the interval of values for a performance metric as occurring in the
real system is shown. This performance metric could be the end-to-end delay
of a system, the utilization of a computation or communication resource, or the
occupation of a channel buffer, for instance. Different performance analysis methods
now differ regarding the values that can be obtained.
When taking measurements of the real system, the measured values only
represent a subset of all possible values. Most likely, due to insufficient coverage of
corner cases and the limited number of measurement samples, the interval bounds
can only be estimated based on the measurements. This observation applies to
simulation as well. Best-case and worst-case analysis methods take a different
approach by providing safe results about the interval bounds, i.e. upper and lower
bounds on the worst-case and best-case behavior, respectively. On the other hand,
usually not all parts of a system can be accurately modeled. In that case, (safe)
optimistic and pessimistic assumptions need to be made, leading to bounds on
system performance measures that are not tight. Finally, also probabilistic methods
are used to provide quantitative statements about system behavior. In the following,
we take a closer look at simulation and best-case/worst-case analysis due to their
frequent application in KPN design flows.
Simulation is presumably the most frequently used method for performance
analysis. This is reflected by the availability of a wide range of simulation tools that
are applicable to different levels of abstraction. The most accurate but also slowest
class are cycle-accurate simulators. Instruction-accurate simulators (also referred to
as instruction-set simulators or virtual platforms) provide a good trade-off between
speed and accuracy which allows entire MPSoCs to be modeled and simulated.