Methods and Tools for Mapping Process Networks onto Multi-Processor Systems-On-Chip - Signal Processing Systems - page 853

Generally, KPN design flows for MPSoCs respect the four design phases of the
Y-chart: system specification, performance analysis, design space exploration, and
system synthesis, as shown in Fig. 1 .
Based on these four phases, the design process can be described as follows:
The starting point of the design flow is a parallelized KPN specification of the
application. In this specification, the coarse-grain data and functional parallelism of
the application is made explicit. Fine-grained word or instruction-level parallelism
can effectively be handled by today's compilers. Usually, the KPN is manually
specified by the programmer. There are, however, also tools available that allow
deriving a KPN from sequential programs, such as the Compaan [ 37 ] and pn [ 67 ]
tools. KPN design flows usually provide a functional simulation capability that
enables the execution of KPN specification on a standard single-processor machine
in a multi-tasking environment. Due to the determinacy of KPNs, the timing-
independent functionality of the application can be validated this way.
Second, the architecture needs to be specified. This is frequently done in
form of a system-level specification describing the architectural resources, such as
processors, memories, interconnects, and I/O devices. This specification can either
describe a fixed MPSoC or the template of a configurable MPSoC platform. In both
cases, the architecture specification needs to contain all the information required for
design space exploration and performance analysis. In the case of a configurable
platform, the architecture specification is also the basis for the synthesis of the
final target platform later in the design flow. Hence, it needs to contain information
required by the RTL synthesis tool, such as references to VHDL or Verilog code of
hardware components, complete IP blocks, and configuration files.
The application and architecture specification phase is followed by defining a
mapping of the application onto the architecture. In this step, processes are bound
to processors and channels are bound to communication paths containing memories
and interconnects. In addition, the scheduling and arbitration policies for shared
resources are defined.
Usually, the final mapping is the result of a design space exploration, which
is done based on the system performance analysis. The methods applied for
performance analysis range from simple back-of-the-envelope calculations to for-
mal analysis methods, simulations, and measurements. In KPN design flows,
performance analysis during design space exploration is possible and is usually done
at a rather high level of abstraction. As shown in the next section, different methods
targeted towards KPN applications have been proposed in this context that achieve
high accuracy within short analysis times. Being able to defer the use of simulation
or measurements until late in the design cycle is one of the key advantages of KPN
design flows.
After manual or automated design space exploration, the system is finally imple-
mented by making use of appropriate synthesis techniques. For this purpose, KPN
design flows feature powerful synthesis tools that implement a system based on the
application, architecture, and mapping specification in software, hardware, or both
hardware and software. Clearly, this is a key advantage of KPN design flows because