DSP Systems Using Three-Dimensional Integration Technology - Signal Processing Systems - page 839

MB in Bank 0 MB in Bank 1

off-set

off-set

Candidate MB

MB in Bank 0 MB in Bank 1

y off-set N- y off-set

Top MB in bank 0

x off-set N- x off-set

Top MB in bank 1

Bottom MB in bank 0

x off-set N-x off-set

Bottom MB in bank 1

Fig. 11 An example to illustrate the calculation of memory access address to fetch one candi-

date MB

The candidate MB spans the last N y off − set rows in the two top MBs, and the

first y off − set rows in the two bottom MBs, as illustrated in Fig. 11 . Hence, we can
correspondingly determine the column addresses. Finally, we should determine the
configuration data for the two barrel shifters (as shown in Fig. 9 ) that forms one row
in the candidate MB at a time. In this context, we can calculate

−

|

| , ≥

x MV % N x MV 0

x of f − set = (9)

−| | , <

N x MV % N x MV 0

For each row read from the reference MBs on the left as shown in Fig. 11 , the barrel
shifter will shift the data towards left by x off − set pixels; for each row read from the
reference MBs on the right as shown in Fig. 11 , the barrel shifter will shift the data
towards right by N

x off − set pixels. By implementing the above simple calculations
in the DRAM domain, the 3D stacked DRAM can readily deliver the candidate MB
to the motion estimation engine on the logic die, while the motion estimation engine
only needs to supply the current motion vector and the position of the current MB.

−

6.3 Performance Evaluation

In the H.264/AVC coding standard, the size of each MB is 16 × 16 and the search

region is set 32 080). Assuming that the luminance

density of each pixel uses 8 bits, each 2-bank frame DRAM has a data I/O bandwidth

× 32 for HDTV1080p (1 , 920 × 1 ,