DSP Systems Using Three-Dimensional Integration Technology - Signal Processing Systems - page 835

Reference Frame DRAM
Bank 1
Bank 0

0 1 0

Search region

0 1 0

Candidate MB

0 1 0

Total 9 MBs from the reference frame

Fig. 8 Frame memory organization for row-by-row data delivery when S BW = S HW = 3

Bank 0 Bank 1

Candidate MB

N D N D

One row

Barrel shifter Barrel shifter

0 0

A row in candidate MB

N D

To logic die through TSVs

Fig. 9 Combine the data from two banks to form a row in candidate MB

luminance intensity data of one row within a candidate MB to the logic die. In
current design practice, a DRAM chip usually consists of multiple banks, which can
be accessed independently, in order to improve the data access parallelism. Since
each candidate MB at most spans 2

2 MBs within the search region and each row
in a candidate MB at most spans two MBs in reference frame, we store each image
frame in two banks that alternatively store all the MBs row-by-row. For example,
suppose each MB is 16

×

× 16 and the search region is 32 × 32, then we have S BW =

S HW = 3, as illustrated in Fig. 8 , where the numbers (i.e., either 0 or 1) within the

nine MBs indicate the index of the two DRAM banks.
Given the current MB and motion vector, the candidate MB from the search
region can be readily retrieved row-by-row. Since one DRAM word-line contains
multiple consecutive rows within the same search region, once each DRAM word-
line is activated and the data of the entire word-line are latched in the sense
amplifiers, multiple rows within the search region can be sent to the logic die
before we switch to another word-line. Assume luminance intensity of every pixel
is represented by D bits, as shown in Fig. 9 , each clock cycle two DRAM banks
delivers two N -pixel rows within the search region, which are further shifted and
combined to form one row in the candidate MB according to the present motion
vector.