Digital Signal Processing Reference
In-Depth Information
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Current
Frame
Video
Buffer
DCT
Q
VLC
Bit
stream
Motion
Estimation
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Reference
Frame
Motion
Compensation
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Intra
Predication
Intra
Predication
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Reconstructed
Frame
De-blocking
Filter
IDCT
IQ
Fig. 7
H.264/AVC encoder structure
the matching functions between the current image macroblock (MB) and all the
candidate MBs inside a confined area in the reference image frame(s). Hence, video
encoding demands the simultaneous storage of several or many image frames in
digital memory.
In current design practice, due to limited on-chip SRAM storage resources, all the
current and reference image frames are stored in an off-chip high-capacity memory,
most likely a DRAM, and on-chip SRAMs are used as buffers to streamline video
encoding. Nevertheless, on-chip SRAM buffers still tend to occupy more than half
estimation. As the video resolution and frame rate continue to increase and multi-
frame-based motion estimation is being widely used, memory storage and access
will inevitably continue to remain as the most critical issue in video encoder IC
design.
It is very intuitive that 3D memory stacking can be the most viable option
to address this issue and hold a great promise to largely improve overall video
encoder performance in terms of silicon area and energy efficiency. In this section,
we quantitatively evaluate the potential using H.264/AVC encoder design as a test
vehicle.
6.1
H.264 Video Encoding Basics
As the latest video coding standard of ITU and ISO Moving Picture Experts
due to its excellent video compression efficiency. Figure
7
illustrates the typical
H.264/AVC encoder structure. Each frame is processed in the unit of MB with
asizeof16
16, each of which is encoded in either intra or inter mode. In the
intra mode, the predicted MB is formed from pixels in the current frame that have
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