DSP Systems Using Three-Dimensional Integration Technology - Signal Processing Systems - page 829

2D SRAM Single-Vth 2D DRAM Multi-Vth 2D DRAM

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

512KB 1MB 2MB 4MB

Fig. 4 Comparison of access latency of 2D SRAM, 2D single-V th DRAM, and 2D multi-V th
DRAM at 65 nm node

Single-Vth 3D DRAM Multi-Vth 3D DRAM

4.5

4

3.5

3

2D SRAM
(1.99ns)

2.5

2

1.5

1

0.5

0

1-layer 2-layer 4-layer 8-layer

Fig. 5 Comparison of 2 MB L2 cache access latency as we increase the number of DRAM dies

L2 cache, multi-V th DRAM L2 cache already excels its SRAM counterpart in terms
of access latency, even without using 3D to further reduce global routing delay. This
essentially agrees with the conclusions drawn from a recent work on embedded SOI
DRAM design [ 4 ] , which shows that embedded SOI DRAM can achieve shorter
access latency than its SRAM counterpart at a capacity as small as 256 kB.
Figure 5 further shows that, when we use the 3D DRAM design strategy
presented in Sect. 4 to implement a 2 MB L2 cache, the access latency advantage
of multi-V th 3D DRAM over 2D SRAM will further improve as we increase the
number of DRAM dies. This is mainly because, as we stack more DRAM dies, the
footprint and hence latency incurred by global routing will accordingly reduce.