Digital Signal Processing Reference
In-Depth Information
Massive logic-memory interconnect bandwidth
Algorithm Design
Space Exploration
Logic Architecture
Design
Application-Aware 3D
Memory Architecture Design
Fig. 1
Joint design methodology for 3D logic-memory integrated application-specific DSP ICs
leveraging the massive logic-memory interconnect bandwidth, we can customize
the memory architecture and storage organization geared to the specific signal
processing algorithm, leading to further potential to improve the overall system
performance. Figure
1
illustrates the close coupling among signal processing
algorithm, logic architecture, and 3D memory architecture design inherent in 3D
logic-memory integrated application-specific DSP IC design.
Although specific materializations of the above joint design will certainly vary
for different DSP algorithms, we believe that the following intuitive general guide-
lines can help designers to explore system design optimization opportunities:
We should always fully analyze the memory access characteristics of the specific
DSP algorithm, and try to accordingly customize the 3D memory architecture and
logic-memory interconnect. This could help to greatly reduce the memory access
energy consumption and/or maximize the overall signal processing system speed
and parallelism.
It is highly desirable to explore the potential of trading memory storage capacity
for improving signal processing performance and/or computational efficiency.
Some signal processing algorithms, which may be considered as infeasible due to
their demand for large memory, could possibly become the most efficient options
under the 3D logic-memory integration framework.
Besides straightforward data storage, the 3D stacked memory could also be
used to realize functions like table look-up or content addressable storage. For
many signal processing algorithms, particularly those involving a significant
amount of search operations, embedding table look-up or content address storage
functions in the 3D memory could potentially achieve noticeable overall system
performance.
To further demonstrate the design of 3D logic-memory integrated DSP systems,
the remainder of this chapter presents two case studies in the context of both
programmable digital signal processor and application-specific DSP IC. As the
mainstream high capacity memory technology, DRAM appears to be the favorable
option for the 3D logic-memory integration. Hence, in the following, we first present
a practical 3D DRAM design strategy that could leverage 3D integration to improve
DRAM design itself, then we will present the two case studies, including a 3D
integrated VLIW digital signal processor and a 3D integrated H.264 video encoder.
