DSP Systems Using Three-Dimensional Integration Technology - Signal Processing Systems - page 821

it is already being used in many commercial products, noticeably in cell
phones [ 26 , 63 ] . Its major limitation is very low inter-die interconnect density
(e.g., only few hundreds of inter-die bonding wires) compared to the other
emerging 3D integration technologies.
2. Transistor build-up 3D technology : It forms transistors inside on-chip intercon-
nect layer [ 3 ] , on poly-silicon films [ 18 ] , or on single-crystal silicon films [ 38 ,
39 ] . Although a drastically high vertical interconnect density can be realized, it
is not readily compatible to existing fabrication processes and is subject to severe
process temperature constraints that tend to dramatically degrade the circuit
electrical performance.
3. Monolithic, wafer-level, back-end-of-the-line (BEOL) compatible 3D technol-
ogy : It is enabled by wafer alignment, bonding, thinning and inter-wafer intercon-
nections [ 53 ] . Realized by through silicon vias (TSVs), inter-die interconnects
can have very high density. The TSVs can be formed before/during bonding
(via-first) or after bonding (via-last) [ 52 ] .

Among the above three different categories of 3D integration technologies,
wafer-level BEOL-compatible 3D integration appears to be the most promising 3D
integration for high-volume production and is quickly becoming mature because of
tremendous recent research efforts from both academia and industries [ 8 , 12 , 33 , 44 ,
47 , 53 , 56 , 57 , 61 , 62 ] . For example, SEMATECH [ 68 ] , the biggest semiconductor
technology research and development consortium, launched its 3D program in
early 2005. It has already generated a comprehensive cost-model and a draft of
a 3D roadmap for the International Technology Roadmap for Semiconductors
(ITRS) [ 34 ] , and begun tool and process benchmarking.
From IC design perspective, vertical interconnects enabled by 3D integration
technology, particularly wafer-level BEOL-compatible 3D integration, provide
several distinct advantages in a straightforward manner, including:

￿ Integration of disparate technologies : Fabrication processing technologies spe-

cific to functions such as DRAM and RF circuits are incompatible with that
of high performance logic CMOS devices. Converging these into a single
2D chip inevitably results in performance compromises (e.g., the density loss
of embedded DRAM [ 54 ] ). Obviously, 3D integration technology provides a
natural vehicle to enable independent optimal fabrication and integration of these
functions.

￿ Massive bandwidth : 3D integration can provide a massive vertical inter-die inter-

connect bandwidth. This can enable a very high degree of operational parallelism
for improving the system performance and/or reducing power consumption.
Meanwhile, this makes it possible to carry out a significant amount of cross-die
co-design and co-optimization.

￿ Wire-length reduction : Expanding from 2D to 3D domain, we may possibly

replace a lateral wire of tens or hundreds of microns with a 2-3 mtall

vertical via. Since interconnects play an important role in determining overall
system speed and power consumption [ 15 , 29 ] , such wire-length reduction can
significantly improve the IC system performance.

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