Digital Signal Processing Reference
In-Depth Information
DSP Systems Using Three-Dimensional
Integration Technology
Tong Zhang, Yangyang Pan, and Yiran Li
Abstract As three-dimensional (3D) integration technology becomes mature and
starts to enter mainstream markets, it has attracted exploding interest from integrated
circuit and system research community. This chapter discusses and demonstrates the
exciting opportunities and potentials for digital signal processing (DSP) circuit and
system designers to exploit 3D integration technology. In particular, this chapter
advocates a 3D logic-DRAM integration design paradigm and discusses the use
of 3D logic-memory integration in both programmable digital signal processors
and application-specific digital signal processing circuits. To further demonstrate
the potential, this chapter presents case studies on applying 3D logic-DRAM
integration to clustered VLIW (very long instruction word) digital signal processors
and application-specific video encoders. Since DSP systems using 3D integration
technology is still in its research infancy, by presenting some first discussions and
results, this chapter aims to motivate greater future efforts from DSP system research
community to explore this new and rewarding research area.
1
Introduction
Three-dimensional (3D) integration has recently attracted tremendous interest from
global semiconductor industries and is expected to lead to an industry paradigm
shift [ 21 , 52 ] . The family of 3D integration technology includes packaging-based 3D
integration such as system-in-package (SiP) and package-on-package (PoP), die-to-
die and die-to-wafer 3D integration, and wafer-level back-end-of-the-line (BEOL)-
compatible 3D integration. In general, all the 3D integration technologies would
offer many potential benefits, including multi-functionality, increased performance,
reduced power, small form factor, reduced packaging, flexible heterogeneous
T. Zhang ( ) ￿ Y. P a n ￿ Y. L i
Rensselaer Polytechnic Institute, Troy, NY, USA
e-mail: tzhang@ecse.rpi.edu ; pany2@rpi.edu ; liy16@rpi.edu
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