Digital Signal Processing Reference
In-Depth Information
V
i
V
o
C
H
S/H
b
V
o
V
i
S
H
Fig. 2
(
a
) A sample and hold circuit. (
b
) Illustration of S/H operation
The S/H can be considered as an ideal impulse sampler followed by a filter with
a frequency response of
sinc
(
π
/
)
(
)=
(
)
/
spectrum is modified because of the droop with frequency caused by the sinc
f
f
s
,where
sinc
x
sin
x
/
2, the input signal
−
.
is attenuated by the factor 0.64 or
9 dB. At the sampling frequency
f
s
the output
of the ideal S/H is zero. The arrows in Fig.
3
represent the fundamental signal and
the images of a sine wave of frequency
f
s
3
/
ω
=
π
/
6 Hz corresponding to
3inthe
discrete-time domain.
The circuit is also called a track and hold circuit when the control signal has such
a duty cycle that the switch is closed for more time than it is open. Many integrated
circuit ADCs include a S/H circuit internally. Such ADCs are also called sampling
A/D converters.
Various performance parameters and nonideality measures are used to character-
1. Tracking speed in the sample mode. There are both small-signal and large-signal
limitations due to a finite bandwidth and limited slew rate.
2. Sample to hold transition error occurs when the S/H goes from sample mode to
hold mode. Opening of the switch is not instantaneous, and the delay may be
different for each switch operation. Charge injection during the sample to hold
