General-Purpose DSP Processors - Signal Processing Systems - page 764

real-time systems where real-time constraint is determined by the repetition period
of the algorithm, we can assume that DSP systems and, in particular, real-time DSP
systems contain mainly repetitious application of data-driven behaviors defined by
mathematical algorithms under strict timing constraints [ 29 ] .
This implies that DSP processors are designed for repetitive, numerically inten-
sive tasks. On the other hand, often DSP applications define two main requirements:
timing and error. The timing requirement dictates that a sequence of operations
defined by the algorithm in hand must be performed in a given time. In addition,
error of the results must be less than specified, i.e., accuracy of computations must
fulfill the requirements. Therefore, we can expect that DSP processors contain
features to improve the accuracy and performance of computations according to
DSP algorithms. In addition, as the processed signals often represent real world
physical signals, there is need to interface the processor to various peripheral
devices, e.g., A/D and D/A, to receive and send digital signals. In particular, in
real-time systems, there is need to transfer data in and out with constant data rate
requirements. Modern DSP processors often contain various peripheral devices for
easy interfacing.
As many of the traditional DSP algorithms contain computation of sum of
products, e.g., FIR filtering being the traditional example; filtered signal y n is
obtained with aid of an N -tap FIR filter as

N 1

i = 0 c i x n − 1

−

y n = (1)

where x n is the input sample at time instant n and c i is the filter coefficient. As
multiplication is often used, a fast multiplier has been an integral part of DSP
processor architecture. Although the first commercially available DSP processor,
Intel 2920 [ 20 , 44 ] , did not have a hardwired multiplier unit at all. The sum of
products computation indicates accumulation, thus multiply-accumulate (MAC) is
advantageous for DSP applications. In particular, single cycle multiply-accumulate
instructions have been seen in DSP processors. Another important property is high
memory bandwidth for feeding the arithmetic units with operands from memory. For
this purpose, multiple-access memory architectures are used, which allow parallel
instruction fetch and operand accesses. In addition, specialized addressing modes
can improve the memory related performance as well as dedicated address genera-
tion units. DSP processors often contain specialized execution control mechanisms;
in particular, efficient looping capabilities reduce the overhead due to repetitive
execution. Specialized features to improve numerical accuracy are also present
as accuracy of results is often one of the main criteria set by DSP applications.
Finally, as DSP systems are often processing data representing real world signals,
input/output interfaces and different peripherals are needed.