Digital Signal Processing Reference
In-Depth Information
A new trend in DSP systems is to use GPGPU for signal processing. GPGPU
stands for General-Purpose computation on Graphics Processing Units. Graphics
Processing Units (GPUs) are high-performance many-core processors that can be
used to accelerate a wide range of applications. For example, authors in [ 18 ] have
demonstrated a GPU-based high speed LDPC decoder implementation. Authors
in [ 73 ] and[ 74 ] have developed a high throughput MIMO detector and a 3GPP
LTE Turbo decoder using GPU.
4
Further Reading
This chapter serves as a brief introduction to the application-specific accelerators
for communications. For more detailed discussion on the VLSI signal processing
system design and implementation, readers are encouraged to read the following
book [ 42 ] . For more information on the software/hardware co-design as well as the
hardware accelerators for 3G/4G wireless systems, one can read the following dis-
sertations [ 9 , 50 ] . Finally, major DSP processor vendors such as Texas Instruments,
Analog Devices, and Freescale provide many application notes about their DSP
hardware accelerators [ 3 , 22 , 63 ] .
Readers are also advised to look at several other chapters of this handbook. For
example, Gustafsson et al. [ 29 ] discusses the fundamental computer arithmetic,
Tak ala [ 58 ] talks about the general-purpose DSP processors, Liu and Wang [ 37 ]
introduces the application-specific instruction set DSP processors, and Zhang et
al. [ 77 ] discusses the three-dimensional DSP systems.
Acknowledgements The authors at Rice University would like to thank Nokia, Nokia Siemens
Networks (NSN), Xilinx, and US National Science Foundation (under grants CCF-0541363, CNS-
0551692, CNS-0619767, EECS-0925942 and CNS-0923479) for their support of this work.
References
1. Alamouti, S.M.: A simple transmit diversity technique for wireless communications. IEEE
Journal on Selected Areas in Communications 16 (8), 1451-1458 (1998)
2. Amiri, K., Cavallaro, J.R.: FPGA implementation of dynamic threshold sphere detection for
MIMO systems. In: IEEE Asilomar Conf. on Signals, Syst. and Computers, pp. 94-98 (2006)
3. Analog Devices: The SHARC processor family.
http://www.analog.com/en/embedded-processing-dsp/sharc/processors/index.html (2009)
4. Bahl, L., Cocke, J., Jelinek, F., Raviv, J.: Optimal decoding of linear codes for minimizing
symbol error rate. IEEE Transactions on Information Theory IT-20 , 284-287 (1974)
5. Bass, B.: A low-power, high-performance, 1024-point FFT processor. IEEE Journal of Solid-
State Circuits 34 (3), 380-387 (1999)
6. Berrou, C., Glavieux, A., Thitimajshima, P.: Near Shannon limit error-correcting coding and
decoding: Turbo-codes. In: IEEE Int. Conf. on Commun., pp. 1064-1070 (1993)
 
 
 
 
 
 
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