Digital Signal Processing Reference
In-Depth Information
DMA
DSP
IF
L-Mem
Interconnection
network
L
n
-
λ
mn
-
-
+
+
+
PE
1
PE
2
PE
z
. . .
+
+
+
L'
n
Interconnection
network (Inverse)
Fig. 31
Semi-parallel LDPC decoder accelerator architecture. Multiple PEs (number of
z
)areused
to increase decoding speed. Variable messages are stored in L-memory and check messages are
stored in
-memory. An interconnection network along with an inverse interconnection network
areusedtoroutedata
Λ
As an example, a multi-standard semi-parallel LDPC decoder accelerator archi-
multiple PEs are used to process multiple check rows simultaneously. As with Turbo
decoding, LDPC decoding is also based on an iterative decoding algorithm. The
iterative decoding flow is as follows: at each iteration, 1
z
APP messages, denoted
as
L
n
are fetched from the L-memory and passed through a permuter (e.g. barrel
shifter) to be routed to
z
PEs (
z
is the parallelism level). The soft input information
λ
mn
is formed by subtracting the old extrinsic message
×
Λ
mn
from the APP message
L
n
. Then the PEs generate new extrinsic messages
Λ
mn
and APP messages
L
n
,and
store them back to memory. The operation mode of the LDPC accelerator needs to
be configured in the beginning of the decoding. After that, it should work without
DSP intervention. Once it has finished decoding, the decoded bits are passed back
to the DSP processor. Figure
32
shows the ASIC implementation result of this
decoder (VLSI layout view) and its power consumption for different block sizes.
As the block size increases, the number of active PEs increases, thus more power is
consumed.
3
Summary
Digital signal processing complexity in high-speed wireless communications is
driving a need for high performance heterogenous DSP systems with real-time
processing. Many wireless algorithms, such as channel decoding and MIMO
