Application-Specific Accelerators for Communications - Signal Processing Systems - page 752

MEM MAP

MEM MAP

DSP
Core

MEM MAP

Interleaver

Fig. 26 Turbo decoder accelerator architecture. Multiple MAP decoders are used to support
high throughput decoding of Turbo codes. Special function units such as interleavers are also
implemented in hardware

based on the iterative message passing algorithms. Thus, a Turbo accelerator may
need more communication and control coordination with the DSP host processor.
For example, the interleaving addresses can be generated by the DSP processor
and passed to the Turbo accelerator. The DSP can monitor the decoding process
to decide when to terminate the decoding if there are no more decoding gains.
Alternately, the Turbo accelerator can be configured to operate without DSP
intervention. To support this feature, some special hardware such as interleavers
have to be configurable via DSP control registers. To decrease the required bus
bandwidth, intermediate results should not be passed back to the DSP processor.
Only the successfully decoded bits need to be passed back to the DSP processor, e.g.
via the DSP DMA controller. Further, to support multiple Turbo codes in different
communication systems, a flexible MAP decoder is necessary. In fact, many
standards employ similar Turbo code structures. For instance, CDMA, WCDMA,
UMTS, and 3GPP LTE all use an eight-state binary Turbo code with polynomial (13,
15, 17). Although IEEE 802.16e WiMax and DVB-RCS standards use a different
eight-state double binary Turbo code, the trellis structures of these Turbo codes are
very similar as illustrated in Fig. 27 . Thus, it is possible design multi-standard Turbo
decoders based on flexible MAP decoder datapaths [ 38 , 47 , 57 ] . It has been shown
in [ 57 ] that the area overhead to support multi-codes is only about 7%. In addition,
when the throughput requirement is high, e.g. more than 20 Mbps, multiple MAP
decoders can be activated to increase the throughput performance.
In summary, due to the iterative structures, a Turbo decoder needs more Gflops
than what is available in a general-purpose DSP processor. For this reason, Texas
Instruments' latest C64x DSP processor integrates a 2 Mbps 3G Turbo decoder
accelerator in the same die [ 65 ] . Because of the parallel and recursive algorithms and
special logarithmic arithmetics, it is more cost effective to realize a Turbo decoder
in hardware.