Digital Signal Processing Reference
In-Depth Information
a
RMC 2
RMC 2
RMC 1
W
RMC 2
RMC 1
RMC 2
RMC 1
Received
sequence
...
...
FMC
FMC
FMC
FMC
b
M
U
X
FBMC
FMC
RAM
L
a
(
u
)
L
c
(
y
u
)
L
c
(
y
c1,2
)
ˆ
ACSA x 8
LLRC
Buffer
M
U
X
RBMC
1
L
e
(
u
)
ˆ
RMC 1
RBMC
2
RMC 2
Fig. 23
Sliding window MAP decoder.
(a)
An example of sliding window MAP algorithm,
where a dummy RMC is performed to achieve the initial
β
metrics.
(b)
MAP decoder hardware
architecture
the reverse (or backward) recursions (dummy RMC 1 and effective RMC 2), and
one for forward recursion (FMC). Each recursion unit contains parallel ACSA units.
After a fixed latency, the decoder produces the soft LLR outputs on every clock
Another key component of Turbo decoders is the interleaver. Generally, the
interleaver is a device that takes its input bit sequence and produces an output se-
quence that is as uncorrelated as possible. Theoretically a random interleaver would
have the best performance. But it is difficult to implement a random interleaver in
hardware. Thus, researchers are investigating pseudo-random interleavers such as
the row-column permutation interleaver for 3G Rel-99 Turbo coding as well as the
these two types of pseudo-random interleavers is the capability to support parallel
Turbo decoding. The drawback of the row-column permutation interleaver is that
memory conflicts will occur when employing multiple MAP decoders for parallel
decoding. Extra buffers are necessary to solve the memory conflicts caused by the
an information block length
N
,the
x
-th QPP interleaved output position is given by
f
2
x
2
Π
(
x
)=(
+
f
1
x
)
mod
N
,
0
≤
x
,
f
1
,
f
2
<
N
.
(16)
