Application-Specific Accelerators for Communications - Signal Processing Systems - page 746

ACS Switch ACS Switch ACS

Fig. 17 Radix-8 ACS architecture

Register
Arrays

Branch
Metric
Calc.

Radix - N
ACS
Arrays

E
M
I
F

D
M
A

DSP Core

Survivors &
Trace Back

DSP Processor

Viterbi Decoder Accelerator

Fig. 18 A generic Viterbi decoder accelerator architecture. Data movement between DSP proces-
sor and accelerator is via DMA. Fully-parallel ACS function units are used to support high speed
decoding

generic Viterbi decoder accelerator is shown in Fig. 18 . Although a pure software
approach is feasible for a modern DSP processor, it is much more cost effective
to implement the Viterbi decoder with a hardware accelerator. The decoder can be
memory mapped to the DSP external memory space so that the DMA transfer can
be utilized without the intervention of the host DSP. Data is passed in and out is in
a pipelined manner so that the decoding can be simultaneously performed with I/O
operations.

2.3.2 Turbo Decoder Accelerator Architecture

Turbo codes are a class of high-performance capacity-approaching error-correcting
codes [ 6 ] . As a break-through in coding theory, Turbo codes are widely used in many
3G/4G wireless standards such as CDMA2000, WCDMA/UMTS, 3GPP LTE, and
IEEE 802.16e WiMax. However, the inherently large decoding latency and complex
iterative decoding algorithm have made it rarely being implemented in a general-
purpose DSP. For example, Texas Instruments' latest multi-core DSP processor
TI C6474 employs a Turbo decoder accelerator to support 2 Mbps CDMA Turbo
codes for the base station [ 65 ] . The decoding throughput requirement for 3GPP
LTE Turbo codes is to be more than 80 Mbps in the uplink and 320 Mbps in the