Application-Specific Accelerators for Communications - Signal Processing Systems - page 741

Tabl e 2 FPGA resource
utilization for sphere detector

Xilinx Virtex-4 xc4vfx
100-12ff1517 Device

Number of Slices 4065/42176 (9%)

Number of FFs 3344/84352 (3%)

Number of Look-Up Tables 6457/84352 (7%)

Number of RAMB16 3/376 (1%)

Number of DSP48s 32/160 (20%)

Max. Freq. 125.7 MHz

Fig. 10 The K -best MIMO detector architecture: the intermediate register banks contain the
sorting information as well as the other values, i.e. R matrix

sphere detection. However, it has a fixed complexity and relatively straightforward
architecture. In this section, we briefly introduce the architecture [ 28 ] to implement
the K -best MIMO detector. As illustrated in Fig. 10 , the PE elements at each stage
compute the Euclidean norms of ( 6 ) , and find the best K candidates, i.e. the K
candidates with the smallest norms, and pass them as the surviving candidates to
the next level. It should be pointed out that the Eq. ( 2 ) can be decomposed into
separate real and imaginary parts [ 28 ] , which would double the size of the matrices.
While such decomposition reduces the complex-valued operations of nodes into
real-valued operations, it doubles the number of levels of the tree. Therefore, as
shown in Fig. 10 , thereare8 K -best detection levels for the 4-antenna system.
By selecting the proper K value, the real-value decomposition MIMO detection
will not cause performance degradation compared to the complex-value MIMO
detection [ 41 ] .
In summary, both depth-first and K-best detectors have a regular and parallel
data flow that can be efficiently mapped to hardware. The large amount of required
multiplications makes the algorithm very difficult to be realized in a DSP processor.
As the main task of the MIMO detector is to search for the best candidate in a very
short time period, it would be more efficient to be mapped on a parallel hardware
searcher with multiple processing elements. Thus, to sustain the high throughput
MIMO detection, an MIMO hardware accelerator is necessary.

2.3 Channel Decoding Accelerators

Error correcting codes are widely used in digital transmission, especially in wireless
communications, to combat the harsh wireless transmission medium. To achieve
high throughput, researchers are investigating more and more advanced error cor-