FPGA-Based DSP - Signal Processing Systems - page 717

a

Program
Counter Main Memory

Memory Crossbars

Scalar
Core

Instruction
Memory

Memory Unit

b

From MAC chain
(optional)

To MAC chain
(optional)

To/from memory

Scalar In

Load-Store
Buffers

Vector Register
Elements

Lane Local
Memory

Vector Flags

From shift chain
(optional)

Scalar Out

Fig. 17 VIPERS vector processor architecture [ 49 ] . ( a ) VIPERS Softcore vector processor,
( b ) VIPERS vector lane

In this arrangement, the design problem extends beyond using an extensible
instruction set architecture for the GPP to include generation of custom instructions
and wrapper logic for any arbitrary core such that it fits into the Molen architec-
ture [ 22 ] . The Molen architecture reports impressive speed-up for DSP and image
processing applications, reporting MPEG-2 application speedups by a factor of up
to three for a Virtex ® -II Pro FPGA using a PowerPC 403 GPP [ 22 , 37 ] .

4.3.2 VIPERS

The application-specific datapath route for accelerating DSP applications con-
sidered thus far is only one feasible option. The vast levels of simple on-chip
programmable DSP-datapath (see Sect. 3.2 ) resource has driven attempts to achieve
acceleration of critical functions by exploiting highly parallel software processing
architectures using these units. VIPERS is one such approach in this vein [ 49 ] .
VIPERS is a softcore vector processor, the architecture of which is outlined in
Fig. 17 a , with the architecture of each vector lane of the processor shown in Fig. 17 b .
Each vector lane contains an ALU (supporting arithmetic and logical operations,