FPGA-Based DSP - Signal Processing Systems - page 701

ALUT 0

6-input
LUT

8

O

add 0

Switching Logic

DQ

r 0

6-input
LUT

add 1

O

Switching Logic DQ

r 1

ALUT 1

Stratix ® -V adaptive logic module (ALM) Fig. 6

Stratix ® -V Adaptive Logic Module 3.1.2

Whilst the fundamental programmable component of the Xilinx Virtex ® range of
FPGA is the CLB, in the case of Altera Stratix ® FPGA it is the Logic Array Block
(LAB) [ 5 ] . Each of these is composed of ten Adaptive Logic Modules (ALMs).
A simplified schematic of an ALM is shown in Fig. 6 . Asthisshows,ALMsare
based around 6-input LUT components, with a total of eight inputs to two LUTs.
Each ALM can implement up to two combinational functions. An ALM also
includes two programmable registers, two dedicated full adders, a carry chain, a
shared arithmetic chain, and a register chain.
Each ALM can operate in four modes, each of which uses the variety of ALM
resources differently.

1. Normal Mode : Suitable for general logic applications and combinational func-
tions; eight data are input to the combinational logic, which implements two
functions or a single function of up to six inputs.
2. Extended LUT : Suited to implementing HDL “ if-else ” conditional func-
tions; a specific set of seven input functions may be implemented, where the
seven inputs are composed of a 2-to-1 multiplexer fed by two arbitrary five input
functions.
3. Arithmetic : The ALM is used to implement adders, counters, accumulators,
wide parity functions and comparators; two sets of two 4-input LUTs are used,
along with two dedicated full adders, which allow the LUTs to perform pre-adder
logic.
4. Shared Arithmetic : Each ALM implements a 3-input addition, where each of
two LUTs implement either the sum or the carry of three inputs; this mode is
designed for multi-operand addition since it reduces the number of summation
stages by increasing the width of each stage.