FPGA-Based DSP - Signal Processing Systems - page 699

c out

a b

LFG

6

2

O SE

DQ

CLK

C out C out

LFG

6

2

O SE

Slice 1

DQ

Switch
Matrix

Slice 0

CLK

c in

clk

C in C in

Fig. 3 Virtex ® -7 FPGA programmable fabric architecture [ 47 ] . ( a ) Virtex ® -7 CLB Structure,
( b ) Simplified Virtex ® -7 Slice ( upper half )

3.1 FPGA Programmable Logic Technology

Virtex ® -7 Configurable Logic Block

3.1.1

Virtex ® series FPGA are primarily constructed of Configurable Logic Blocks
(CLBs). The structure of a CLB is outlined in Fig. 3 a . As this shows, CLBs are
composed of two slices , each of which contains four Logic Function Generator
(LFG) units, as shown in Fig. 3 b (only the upper two slices are shown, the given
structure is replicated to create the full slice architecture). In Virtex ® , Virtex ® -II
and Virtex ® -II Pro technologies the LFG units had four inputs and one output, but
this increased to five inputs and one output in Virtex ® -4, and further to six inputs
and two outputs in Virtex ® -5 FPGA and beyond [ 47 ] .
The basic slice architecture of Virtex ® -7 contains four sets of: a single 6-input
LFG, a storage element (SE) for registering the data emanating from the LFG, and a
fast carry and switching logic which, coupled with the c out and c in ports on adjacent
sets and slices can be used to cascade sets to implement high performance bit-
parallel adders.
This relatively simple slice structure masks considerable complexity and diverse
modes of operation. The LFGs can operate in one of four modes: as a single 6-
input, 2-output LUT, as two 5-input, 1-output LUTs (assuming common inputs
to the two input LUTs); as a 64 bit distributed RAM (DisRAM), or as a 32
element shift register (SRL). In DisRAM mode a single 64 bit RAM (Fig. 4 a ), may
be realised with numerous such RAMs combined to implement larger or higher
bandwidth RAMs if so desired. This is outlined in Fig. 4 b whichshowsa1bitwide,
64 bit dual-port DisRAM. Larger bandwidth DisRAMs may be created by using
numerous single-bit RAMs in parallel. In the SRL mode, each LFG may implement
an addressable shift register of up to 32 elements in length, and multiple LFGs are
cascadable for implementation of longer shift registers, as outlined in Fig. 5 .