FPGA-Based DSP - Signal Processing Systems - page 694

function, and could be arbitrarily interconnected, they could be used in networks to
implement any digital logic functionality. This vision became incarnate in the Xilinx
XC2064, the world's first FPGA device, in 1985. In the intervening period, the
FPGA has changed markedly and dramatically from the simple “glue-logic” style
devices of the original incarnations to domain-specific heterogeneous processing
platforms comprising microprocessors, multi-gigabit serial transceivers, networked
communications endpoints and vast levels of on-chip computation resource in the
latest generations.
The key motivating factors for choosing FPGA as a target platform for DSP ap-
plications are flexibility, real-time performance and cost. Whilst software processors
allow functional flexibility, the application's real-time performance requirements or
physical constraints placed on the embedded realisation, for example in terms of
size or power consumption, may be beyond that which these can achieve. In such
a situation, unless volumes are sufficiently high, the Non-Recurring Engineering
(NRE) costs associated with creating a customised Application Specific Integrated
Circuit (ASIC) are such that this may not be commercially viable. For such
high performance, low volume DSP systems, the ability of FPGA to host custom
computing architectures tailored to the real-time requirements of the application
and physical requirements of the operating environment, at relatively low cost, is a
key advantage.
The historical perspective of FPGA is as a blank canvas “sea” of programmable
logic ideal for hosting high performance custom circuit architectures. Indeed design
tools which promote this kind of approach are prominent [ 1 , 4 , 6 , 14 , 43 ] . However,
state-of-the-art FPGA are very different devices. They are massively complex
combinations of heterogeneous processing, communication and memory resources
capable of hosting very high performance DSP architectures. Typically they boast
around 50 times the programmable Multiply Accumulate (MAC) processing re-
source of DSP processor s 1 and host custom memory structures ranging from large
capacity, low bandwidth off-chip storage to small, high bandwidth on-chip Static
Random Access Memory (SRAM); combined with the almost limitless levels of
data and task level parallelism available, their potential in place of fixed architecture,
software programmable embedded devices is huge. However, this potential is
only realised if the resources are properly harnessed in a manner which is easily
accessible to application designers. Proper use of resources, in the context of modern
FPGA, means creation of heterogeneous networks of microprocessors with optional
accelerator co-processors [ 3 , 37 , 41 ] and parallel software processing architectures
(i.e. multiple datapaths operating under the control of a single control unit) [ 7 , 49 ]
along with the classic dedicated hardware components.
The complexity of the architectures to be created, coupled with the requirement
to create a new architecture for every new application makes the FPGA system
design problem unique. The keys to success in this process are understanding the
1 Based on comparison of Virtex ® 6 XC6VSX475T with assumed clock rate of 500 MHz and Texas
Instruments TMS3206474 DSP.