Digital Signal Processing Reference
In-Depth Information
OPA=AR+jAI
OPC=CR+jCI
AR
AI
CR
CI
NxN
MUL
NxN
MUL
NxN
MUL
NxN
MUL
IMI
RMR
RMI
IMR
ADD/SUB
ADD/SUB
2Nb
2Nb
OPB=
BR+
jBI
SUB/ADD
SUB/ADD
SUB/ADD
SUB/ADD
Re(MUL)
Im(MUL)
2Nb
2Nb
2Nb
2Nb
ACRR
ACIR
Re(MAC)
Im(MAC)
Re(B-A×C)
Re(B+A×C)
Im(B-A×C)
Im(B+A×C)
Fig. 19
A radix-2 data path for complex data computing
The reference microarchitecture is close to the requirements of the module to be
designed and can execute most micro-operations allocated to the module.
Another method is to design a custom microarchitecture, which is to generate a
custom architecture dedicated for a task flow of an application. This method is used
when there is no reference microarchitecture or the reference microarchitecture is
not good enough. The method is to map one or several CFG (control flow graph,
the behavior flow chart of an application) to hardware. A typical case is to design
accelerator modules for special algorithms, such as lossless compression algorithms,
forward error correction algorithms, or packet processing protocols.
A typical example in Fig.
19
shows an example of a simplified datapath cluster
for complex-data computing in a radio baseband signal processor. N in this figure
is the word length of real or imaginary data. The cluster can execute the following
functions one step in a clock cycle. These functions are computing a FFT butterfly,
iterative computing for complex data multiplication and accumulation, complex data
multiplication, and complex data addition/subtraction.
A Radix-2 decimation in time (DIT) butterfly can be executed in each clock cycle
for FFT. The input data of the butterfly is data OPA
=
+
=
AR
jAI and OPB
BR
