Application Specific Instruction Set DSP Processors - Signal Processing Systems - page 685

modeling, bit accurate modeling, memory accurate modeling, timing budget and
real-time modeling, and finally assembly coding. Firmware design has three starting
points according to the freedom of the design.
If designers have all freedoms including selection of algorithms, the design
will start from design entry 1, the step of algorithm design and selection. For
example, standards of radio baseband modems specify only the transmitter and
do not regulate the implementation of receivers. During the implementation of
radio baseband receivers, we have the freedom to select either a frequency-domain
channel estimator or a time-domain channel estimator according to the cost-
performance trade off, the computing latency, and the hardware architecture. Here
the cost means mostly the computing cost, data access cost, and the memory cost.
For example, some architecture will be suitable for transform and frequency domain
algorithms. High level behavior of a DSP system is modeled based on high precision
data types and a behavior modeling language, such as C.
However, if there is no freedom to select algorithms, a design starts from design
entry 2. A typical example is video decoding for H.264 or audio decoding for
MP3. Algorithms and C code are available from the standard. The C code is based
on floating-point with excessive high data precision. For embedded applications,
hardware with fixed point and limited precision will be used. The design following
entry 2 starts from bit-accurate modeling. In this case, the freedom to decide the
data precision is available. Data or intermediate results can be scaled and truncated
during processing. During the bit accurate modeling phase, data quality control
algorithms, such as data masking to emulate the finite hardware precision, signal
level measurements, and gain control algorithms, will be added to the original
source code.
Freedom of data precision control may not be available in some designs.
When the freedoms of algorithm selection and data precision are not available,
the firmware design entry is 3 in Fig. 18 . In this case, the bit accurate model is
available when the firmware design starts, for example the bit accurate source code
could be from a standard committee. A typical case is the implementation of some
voice decoder, which starts from available bit-accurate C code. Voice is usually
compressed before transfer or storage to minimize the transfer bandwidth or storage
cost. A voice decoder will decompresses the compressed voice and to recover the
voice waveform at the voice user side.
In most ASIP, scratchpad memories instead of cache are used to minimize the
data access latency. The time cost of data access and the memory cost is roughly
exposed during source code profiling. The early estimate of memory cost might not
be correct. Memory cost can be further exposed when the data types are decided
after bit accurate modeling. A memory accurate model can therefore be achieved.
Cache is not much used for embedded DSP computing because cache is expensive
and data access in embedded computing is relatively explicit and predictable.
A memory accurate model is an essential step to expose the data access cycle cost of
scratchpad memories and finally to minimize it. The first step of memory accurate
modeling is to re-model the data access in real hardware based on the constraint of
the on chip memory sizes. After the first step, the extra memory transaction cost