Digital Signal Processing Reference
In-Depth Information
Power efficiency of a system is the average performance over the average power
consumption. Low power ASIP design is the process of minimizing redundant
operations (to minimize the dynamic power) and minimizing the circuit size (to
minimize the static power). When the size of transistors shrinks, power efficiency
and silicon efficiency are more related because the static power is no longer
negligible and even becomes dominant.
In a modern high-end ASIP design, since the memory consumes most of the
power, the design for power efficiency is almost the same as the design of efficient
memory architecture. It is about optimizing the memory partition, minimizing the
memory size, and minimizing memory transactions.
Silicon efficiency of a system is defined as the average performance over
the ASIP silicon area. In general, as discussed previously, low power design is
equivalent to designing for silicon efficiency. The on chip memory size of a silicon
efficient solution is relatively small. If the on chip memory size is too small,
however, the design may induce extra on-chip and off-chip data swapping and
introduce extra power consumption.
Figure
5
gives architecture selection among six popular DSP processor architec-
tures. The single MAC architecture is a typical low cost DSP processor architecture
with single multiplication-and-accumulation unit in datapath. Only one iterative
computing can be executed at a time in the processor. The performance may not
be enough for advanced applications. The complexity handling capability can be
relatively high if the instruction set is advanced. This architecture consumes the
least silicon cost and power consumption is limited.
The dual MAC architecture is a kind of high performance and efficient architec-
ture. There are two multiplication-and-accumulation units in datapath. Two iterative
computations or two steps of an iterative computation can be executed at a time by
Dual-MAC in the processor. By keeping the same complexity handling capability,
the iterative computing performance of a Dual MAC machine can be double.
Compared to the single MAC machine, the silicon cost and power consumption may
be only few percentage higher, so the silicon efficiency and the power efficiency of
a dual MAC machine is much better.
A SIMD (single instruction multiple data) machine can perform multiple opera-
tions while executing one instruction. The computing performance is high. However,
a SIMD machine can handle data level parallel computing only when computation is
regular. While handling irregular operations for complex control functions, a SIMD
machine exposes its weaknesses. Power and silicon efficiency can be very high if a
SIMD machine handles only regular vector data signal processing. In most systems,
SIMD is a slave processor to accelerate signal processing with regular data structure.
A master is used to handle complex control functions. Because control and parallel
data processing are allocated to two processors, extra computing latencies induced
by inter-processor communications should be taken into account.
When requirements on both the computing performance and the complexity
handling are high at the same time, a VLIW (very long instruction word) machine
may be a solution. A VLIW machine can execute multiple operations in one
clock cycle. However, it does not have a data dependency checker in hardware.
Advanced compiler technology must be available together with VLIW technology.
