Digital Signal Processing Reference
In-Depth Information
The ASIP hardware design flow starts from the requirement specification and
finishes after the microarchitecture design. The design of an ASIP is mostly based
on experience. The essential goal of ASIP design flow is to minimize the cost of
design iteration. Design of an ASIP is a risky and expensive business with much
rewarding when the design is successfully implemented.
After specifying the microarchitecture of an ASIP, the VLSI implementation will
be the same as all other silicon backend designs, and can be found from any backend
VLSI book. RTL coding and silicon implementation are out of the scope of the
chapter.
3
Architecture and Instruction Set Design
In this chapter, the design methodology of an ASIP will be refined. Architecture and
assembly instruction set design methods will be introduced.
3.1
Code Profiling
The development of a large application may involve the experiences from hundreds
of people over many years. Application engineers take years to learn and accumulate
system design experience. Unlike application engineers, ASIP designers are hard-
ware engineers who specialize on circuit specification and implementation as well
the design of assembly coding tools. It is impossible that ASIP engineers can really
understand all the design details of an application in a short time.
Source code profiling fills the gap between system design and hardware design.
The purpose of profiling is not to understand the system design; it is rather to
understand the cost of the design including dynamic behavior of code execution
and the static behavior of the code structure, the hardware cost, and the runtime
cost. Source code profiling is a technique to isolate the ASIP design from the design
of applications.
Code profiling can be dynamic or static. Static profiling analyzes the code instead
of running it, so it is data (or stimuli) independent. Static code profiling exposes the
code structure and the critical (maximum, or worst case) execution time.
A static code profiler is based on a compiler frontend, the code analyzer. Code
structure can be exposed in a control flow graph (CFG), the output of the code
analyzer. All run time cost including computing and data access can be assigned
to each branch of the graph and the total costs can be collected and estimated by
accumulating the cost of each path. The critical path with the maximum execution
time should be identified via source code analyzers for ASIP design.
However, a critical path may seldom or never be executed and dynamic profiling
is thus needed. Dynamic profiling is to run the code by feeding selected data stimuli.
Dynamic profiling can expose the statistics of the execution behavior if the stimuli
