Digital Signal Processing Reference
In-Depth Information
Fig. 16
Interaction between the exchange controller and interface controller
The PE CU Interface Controller interfaces with the exchange controller as
Their functions are identical and operational under tight control by the Exchange
Controller. Structurally, each Interface Controller contains address generation logic
for each buffer in the PE CU interface.
Interface controllers are mainly composed of counters and incrementors. The
Interface Controller then reads and writes particles between a buffer pair. The
initiation of buffer accesses by the Interface Controller is controlled by the Exchange
Controller through the write enable and read enable signals. The PE CU interface
makes sure that local particle transfers, from RTB
iu
to RB
i
and from RB
i
to RTB
id
,
are not active when connection between RTB
iu
and RTB
id
is established by the
Exchange Controller. While buffers are being accessed, this interface controller
sets busy flag to the Exchange Controller indicating that the corresponding PE CU
interface is not available. In turn, the Exchange Controller uses this information in
establishing appropriate connection using the Priority Decoder. Once the Exchange
Controller generates write enable and read enable for a particular buffer, each
Interface Controller acknowledges back to the Exchange Controller. The Interface
Controller reads or writes particles until the condition changes or
p
particles are
transferred where
p
is small and constant. A reason for transferring finite number
of particles at any connection is to minimize the non-deterministic latency (
L
CU
1
).
reads particles from FIFO, an additional condition is that it reads if FIFO is not
empty. Formally, possible conditions for terminating the entire particle transfer are:
(1) there are no more particles to read from RTB, or (2) the source PE CU interface
has enough particles. If one of these conditions is met, the Interface Controller
indicates that the operation is completed and returns to wait state.