Arithmetic - Signal Processing Systems - page 602

a 4 a 3 a 2 a 1

a 0

x 0 . x 1 x 2 ... x Wd -1

D D D D

& & & & &

y

z

FA FA FA FA FA

D D D D D

Set

Fig. 26 Serial/parallel multiplier-accumulator

3.3 Vector Merging Adder

The role of the vector merging adder is to add the outputs of the reduction tree. In
general, any carry-propagation adder can be used, e.g., those presented in Sect. 2 .
However, the different input signals to the adders will typically be available at
different delays from the multiplier input values. Therefore is it possible to derive
carry-propagation adders that utilize the different signal arrival times to optimize
the adder delay [ 48 ] .

3.4 Multiply-Accumulate

In many DSP algorithms computations of the form Z A are common. These

can be effectively implemented by simply adding another row corresponding to A in
the partial product array. In many cases this will not increase the number of levels
required.
For sequential operation, the modification of the first stage of the serial/parallel
multiplier as shown in Fig. 26 , makes it possible to add an input Z to be added to the
product at the same level of significance as X .

= XY +

3.5 Multiplication by a Constant

When the multiplier coefficient is known, it is possible to reduce the complexity of
the corresponding circuit. First of all, no circuitry is required to generate the partial
products. Second, there will in general be fewer partial products to add. This can
easily be realized considering the partial product array in Fig. 17 . For the coefficient