Arithmetic - Signal Processing Systems - page 593

Fig. 15 Principle of a
multi-operand adder

X 1 X 2 X 3 X N

Redundant
adders

CPA

the stage is equivalent to the delay of the first stage plus the number of multiplexers
that the carry signal passes through. Hence, the actual values are determined by
the relative adder and multiplexer delays, as well as the fan-out of the multiplexer
control signals.
For each smaller adder in the carry-select adder, it is possible to apply the same
idea of splitting each smaller adder into even smaller adders. For example, each of
the two k 1 bit adders can be split into two k 3 bits and one k 4 bits adders, where k 1 =
k 3 + k 4 , in a similar way. Note, however, that only four smaller adders are required

instead of six as the same two k 3 bits adders can be used. If this is applied until
only 1-bit adders remain, we obtain a conditional sum adder. There are naturally, a
wide range of intermediate adder structures based on the ideas of carry-select and
conditional sum adders.

2.4 Multi-operand Addition

When several operands are to be added, it is beneficial to avoid several carry-
propagations. Especially, when there are delay constraints it is inefficient to use
several high-speed adders. Instead it is common to use a redundant intermediate
representation and a fast final carry-propagation adder (CPA). The basic concept is
illustrated in Fig. 15 .
For performing multi-operand addition, either counters or compressors or a
combination of counters and compressors can be used. A counter is a logic gate that
takes a number of inputs, add them together and produce a binary representation of
the output. The simplest counter is the full adder cell shown in Fig. 1 b . In terms of
counters, it is a 3:2 counter, e.g., it has three inputs and produce a 2-bits output word.
This can be generalized to n : k counters, having n inputs of the same weight and
producing a k bit output corresponding to the number of ones in the input. Clearly,
n and k must satisfy n 2 k .

A compressor on the other hand does not produce a valid binary count of the
number of input bits. However, it does reduce the number of partial products, but at
the same time has several incoming and outgoing carries. The output carries should
be generated without any dependence on the input carries. The most frequently

≤ − 1 or equivalently k ≥ log 2 ( n + 1 )