Coarse-Grained Reconfigurable Array Architectures - Signal Processing Systems - page 573

a b

c d

Fig. 11 4 CGRAs with fixed ISs and fixed RFs,

but with varying interconnects ( a )MIMO;( b ) AVC interpolation; ( c ) Viterbi; ( d ) AVC motion
estimation

DSE results for four microbenchmarks on 4 ×

power is spent in the FUs and in the interconnects, i.e., on the actual computations
and on the transfers of values from computation to computation. The latter two
aspects are really the fundamental parts of the computation to be performed, unlike
the fetching of data or the fetching of code, which are merely side-effects of the fact
that processors consist of control paths, data paths, and memories.

4.2.2 Design Space Exploration Example

Many DSEs have been performed within the ADRES template [ 5 , 11 , 15 , 40 , 46 , 51 ] .
We present one experimental result [ 40 ] here, not to present absolute numbers but to
demonstrate the large impact on performance and on energy consumption that some
design choices can have. In this experiment, a number of different interconnects
have been explored for four microbenchmarks (each consisting of several inner
loops): a MIMO SDR channel estimation, a Viterbi decoder, an Advanced Video
Codec (AVC) motion estimation, and an AVC half-pixel interpolation filter. All of
them have been compiled with the DRESC compiler for different architectures of
which the interconnects are combinations of the four basic interconnects of Fig. 6 ,
in which distributed RFs have been omitted for the sake of clarity.
Figure 11 depicts the relative performance and (estimated) energy consumption
for different combinations of these basic interconnects. The names of the different