Coarse-Grained Reconfigurable Array Architectures - Signal Processing Systems - page 555

typically includes more conditional code than SDR baseband processing. Hence the
design of, e.g., different ADRES architectures for multimedia and for SDR resulted
in different predicate data paths being used, as illustrated in Sect. 4.2.1 .
At this point, it should be noted that the use of predicates is fundamentally not
that different from the use of events or tokens. In KressArray or PACT, events and
tokens are used, amongst others, to determine at run time which data is selected to
be used later in the loop. For example, for a C expression like x + (a>b) ? y
+z:y-z one IS will first compute the addition y+z , one IS will compute
the subtraction y-z , and one IS will compute the greater-than condition a>b .The
result of the latter computation generates an event that will be fed to a multiplexor
to select which of the two other computer values y+z and y-z is transferred to
yet another IS on which the addition to x will be performed. Unlike the muxes in
Fig. 2 b that are controlled by bits fetched from the configuration memory, those
event-controlled multiplexors are controlled by the data path.
In the ADRES architecture, the predicates guard the operations in ISs, and they
serve as enable signals for RF write ports. Furthermore, they are also used to control
special select operations that pass one of two input operands to the output port of
an IS. Fundamentally, an event-controlled multiplexor performs exactly the same
function as the select operation. So the difference between events or tokens
and predicates is really only that the former term and implementation are used in
dynamically scheduled designs, while the latter term is used in static schedules.

3.4 Computational Resources

Issue slots are the computational resources of CGRAs. Over the last decade,
numerous designs of such issue slots have been proposed, under different names,
that include PEs, FUs, ALUs, and flexible computation components. Figure 7
depicts some of them. For all of the possible designs, it is important to know the
context in which these ISs have to operate, such as the interconnects connecting
them, the control type of the CGRA, etc.
Figure 7 a depicts the IS of a MorphoSys CGRA. All 64 ISs in this homogeneous
CGRA are identical and include their own local RF. This is no surprise, as the two
MorphoSys SIMD modes (see Sect. 3.2.1 ) require that all ISs of a row or of a column
execute the same instruction, which clearly implies homogeneous ISs.
In contrast, almost all features of an ADRES IS, as depicted in Fig. 7 b , can be
chosen at design time, and can be different for each IS in a CGRA that then becomes
heterogeneous: the number of ports, whether or not there are latches between the
multiplexors and the combinatorial logic that implements the operations, the set
of operations supported by each IS, how the local registers file are connected to
ISs and possibly shared between ISs, etc. As long as the design instantiates the
ADRES template, the ADRES tool flow will be able to synthesize the architecture
and to generate code for it. A similar design philosophy is followed by the
Silicon Hive tools. Of course this requires more generic compiler techniques than