Digital Signal Processing Reference
In-Depth Information
TinyRISC
Core
Processor
Memory
controller
8×8
Morphosys
CGRA
Double
Frame Buffer
Caches
Configuration
Memory
DMA Controller
Fig. 3
A TinyRISC main processor loosely coupled to a MorphoSys CGRA array. Note that the
main data memory (cache) is not shared and that no IS hardware or registers is are shared between
the main processor and the CGRA. Thus, both can run concurrent threads
sh
ared R
F
I
S
0
I
S
1
I
S
2
I
S
3
Data
Memory
Controller
R
F
1
R
F
0
I
S
4
I
S
5
I
S
6
I
S
7
Data
Memories
(catches or
scratch-pads)
I
S
8
I
S
9
I
S
A
I
S
B
R
F
2
R
F
3
IS
C
IS
D
I
S
E
I
S
F
Fig. 4
A simplified picture of an ADRES architecture. In the main processor mode, the
top row
of ISs operates like a VLIW on the data in the shared RF and in the data memories, fetching
instructions from an instruction cache. When the CGRA mode is initiated with a special instruction
in the main VLIW ISA, the whole array starts operating on data in the distributed RFs, in the shared
RF and in the data memories. The memory port in IS 0 is also shared between the two operating
modes. Because of the resource sharing, only one mode can be active at any point in time
of ISs, executes a loop for which it gets its configuration bits from a configuration
memory. This memory is omitted from the figure for the sake of simplicity.
The drawback of this tight coupling is that because the CGRA and the main
processor mode share resources, they cannot execute code concurrently. However,
this tight coupling also has advantages. Scalar values that have been computed
in non-loop code, can be passed from the main CPU to the CGRA without any
overhead because those values are already present in the shared RFs or in the shared
memory banks. Furthermore, using shared memories and an execution model of
