Multicore Systems on Chip - Signal Processing Systems - page 536

designs. Intel and AMD are still using integrated buses to make the communication
infrastructure on their high-end MPSoC, due to the easier implementation and high
bandwidth provided.
Crossbars are widely used on network hardware like switches and hubs. Some
MPSoC designers have been employing this mechanism to connect processing
elements [ 10 ] . This interconnection approach provides huge performance, allowing
communication between any processing elements and the smallest possible time.
However, high area cost, energy consumption and poor scalability discourage its
employment. AMD Opteron family and Sun Niagara use crossbars to support high
communication bandwidth within their general-purpose processors.
Network-on-chip has been emerging as a solution to couple several processing
elements [ 21 ] . This approach provides high communication parallelism, since
several connecting paths are available for each node. In addition, as the technology
scales, wire delays increase (because of the increased resistance derived form the
smaller cross-section of the wire), and hence shorter wires, as used in NoCs could
soften this scaling drawback. Also, its explicit modular shape positively affects
the processing elements scalability, and can be explored by a power management
technique to support the simple turning off of idle components of the network
on chip. NoC disadvantages include the excessive area overhead and high latency
of the routers. Intel 80-core prototype employs a mesh style network-on-chip
interconnection to supply the communication of its 80 processing elements.

5.2 MPSoC Programming Models

For decades, many ILP exploration approaches were proposed to improve the
processor performance. Most of those works employed dynamic ILP exploration
at hardware level, becoming an efficient and adaptive process used in superscalar
architectures, for instance. Also, traditional ILP exploration free software devel-
opers from the hard task to explicit, in the source code, those parts that can be
executed in parallel. Some works [ 19 ] can even translate code with enough ILP
into TLP, so that more than one core can execute the code, exploiting ILP also at
the single issue core level, when embedded in a multiprocessing device. However,
MPSoC employment relies on manual source code changes to split the parallel parts
among the processing elements. Currently, software developers must be aware of the
MPSoC characteristic like the number of processing elements to allocate the parallel
code. Thus, the sequential programming knowledge should migrate to the parallel
programming paradigm. Due to these facts, parallel programming approaches
have been gaining importance on computing area, since easy and efficient code
production is fundamental to explore the MPSoC processing capability.
Communication between processing elements is needed whenever information
exchange among the threads is performed. Commonly, this communication is based
either on message passing or on shared memory techniques. Message passing
leaves the complex task of execution management to the software description level.