Multicore Systems on Chip - Signal Processing Systems - page 532

4.4 Other MPSoCs

Other MPSoCs have already been released in the market, with different goal
from the architectures discussed before. Sony, IBM and Toshiba have worked
together to design the Cell Broadband Engine Architecture [ 3 ] . The Cell architecture
combines a powerful central processor with eight SIMD-based processing elements.
Aiming to accelerate a large range of application behaviors, the IBM PowerPC
architecture is used as GPP processor. Also, this processor has the responsibility
to manage the processing elements surrounding it. These processing elements,
named as synergistic processing elements (SPE), are built to support streaming
applications with SIMD execution. Each SPE has a local memory, but no hardware
is employed to manage it, which avoid that these memories directly access the
system memory. These facts make the software development for the Cell processor
even more difficult, since the software team should be aware of this local memory,
and manage it at the software level to better explore the SPE execution. Despite
its high processing capability, the Cell processor does not yet have a large market
acceptance due to the intrinsic difficulty to produce software. Sony has lost parts
of the gaming entertainment market after the Cell processor was deployed in the
Playstation console family, since game developers had not enough knowledge to
efficiently explore the complex Cell architecture.
Homogeneous MPSoC organization is also explored in the market, mainly for
personal computers with general-purpose processors, because of the huge amount of
different applications these processors have to face, and hence it is more difficult to
define specialized hardware accelerators. In 2005, Sun Microsystems announced its
first homogeneous MPSoC, composed of up to eight processing elements executing
the full RISC SparcV9 instruction set. UltraSparc T1, also called Niagara [ 11 ] , is
the first multithreaded homogeneous MPSoC, and each processing element is able
to execute four threads concurrently. In this way, Niagara can handle, at the same
time, up to 32 threads. Recently, with the deployment of UltraSparc T2 [ 10 ] , this
number has grown to 64 concurrent threads. Niagara MPSoC family targets massive
data computation with distributed tasks, like the market for web servers, database
servers and network file systems.
Intel has announced its first MPSoC homogeneous prototype with 80 cores,
which is capable of executing 1 trillion floating-point operations per second, while
consuming 62 W [ 21 ] . Hence, the x86 instruction set architecture era could be
broken, since their processing elements is based on the very long instruction word
(VLIW) approach, letting to the compiler the responsibility for the parallelism
exploration. The interconnection mechanism used on the 80-core MPSoC uses a
mesh network to communicate among its processing elements [ 5 ] . However, even
employing the mesh communication turns out to be difficult, due to the great
amount of processing elements. In this way, this ambitious project uses a 20 MB
stacked on-chip SRAM memory to improve the processing elements communication
bandwidth.