Multicore Systems on Chip - Signal Processing Systems - page 530

Samsung S3C6410 Samsung S5PC100

ARM® Cortex™-A8
32 KB/32 KBI/DCache
667/883 MHz
256KB +L2 Cache
NEON

ARM® 1176JZF-S
I/D cache 16KB/16KB
533/667MHz

Multimedia Accelerators

Camera : 4MP

H.264/MPEG4/VC1 Camera IF w/CSI-2

2D/3D Graphics

720p Video Engine

2D/3D Graphics NTSC/PAL NTSC/PAL/HDMI

JPEG CODEC JPEG CODEC

Fig. 12 Samsung S3C6410 and S5PC100 MPSoC block diagrams

decision to achieve efficient multimedia execution. Commonly, the integration of
specific accelerators is used, since this reduces the design time avoiding validation
and testing time.
In 2008, Samsung has launched the most powerful of the Mobile MPSoC family.
At first, S3C6410 was a multimedia MPSoC like OMAP4440. However, after
its deployment in the Apple iPhone 3G employment, it has become one of the
most popular MPSoCs, shipping three million units during the first month after
the launching. Recently, Apple has developed iPhone 3GS, which assures better
performance with lower power consumption. These benefits are supplied by the
replacement of the S3C6410 architectures with the high-end S5PC100 version.
In this subsection, we will explore both architecture highlighting the platform
improvements between S3C6410 and S5PC100. The S5PC100 was the last Samsung
SoC employed by Apple in the iPhone. After that, Apple encapsulates his own chips
in iPhone 4 and 4S, the Apple A4 and Apple A5 chips, respectively. However, these
chips still being fabricated by Samsung.
Following the multimedia-based MPSoC trend, Samsung platforms are com-
posed of several application specific accelerators building heterogeneous MPSoC
architectures. S3C6410 and S5PC100 have a central general-purpose processing
element, in both cases ARM-based, surrounded by several multimedia accelerators
tightly targeted to DSP processing. As can be noticed in Fig. 12 , both platforms
skeleton follows the same execution strategy changing only the processing capa-
bility of their IP cores. This is an interesting design modeling approach, since
while traditional architecture designs suffer for long design/validate/test phases to
build a new architecture, MPSoC ones shorter these design times only by replacing
their low-end cores for high-end ones, creating a new MPSoC architecture. This
can be verified in the Fig. 12 , small platform changes are done from S3C6410
to S5PC100 aiming to increase the MPSoC performance. More specifically, a
nine-stage pipelined ARM 1176JZF-S core with SIMD extensions is replaced for
a 13-stage superscalar pipelined ARM Cortex A8 providing greater computation
capability for general-purpose applications. Besides its double-sized L1 cache