Digital Signal Processing Reference
In-Depth Information
Instructions
CPI
SLE
CycleTime
SHE
CPI
SLE
issue
∝
+
β
ET
SHE
ET
MP
=
Instructions
P
+
γ
CycleTime
MP
.
(6)
(
∝
CPI
SLE
+
β
CPI
SLE
)
If one considers that in the model of the multiprocessor environment, a single
low end processor is not capable of exploiting instruction level parallelism, and
then
∝
=
Instructions
CPI
SLE
CycleTime
SHE
CPI
SLE
∝
issue
+
β
ET
SHE
ET
MP
=
Instructions
P
+
γ
CycleTime
MP
,
(7)
(
0
∗
CPI
SLE
+
1
∗
CPI
SLE
)
Instructions
CPI
SLE
CycleTime
SHE
CPI
SLE
issue
+
β
∝
ET
SHE
ET
MP
=
Instructions
P
+
γ
CycleTime
MP
.
(8)
(
CPI
SLE
)
We are also considering that, as a homogeneous multiprocessor design is
composed of several low-end processors with a very simple organization, those
processors could run at much higher frequencies than a single and complex high-end
processor. Therefore, we will assume that
1
CycleTime
MP
1
CycleTime
SHE
=
K
∗
,
(9)
where
K
is the frequency adjustment factor to equal the power consumption of the
homogeneous multiprocessor with the high-end single processor.
1
P
+
γ
K
CPI
SLE
∝
issue
+
β
CPI
SLE
CPI
SLE
ET
SHE
ET
MP
=
.
(10)
than a multiprocessor-based machine if
ET
SHE
ET
MP
1. This equation also shows that,
although the multiprocessor architecture with low-end simple processors could have
a faster cycle time (by a factor of
K
), that factor alone is not enough to define
Because the high-end processor can execute many instructions in parallel, better
performance improvements can be obtained, as long as ILP is the dominant factor,
instead of TLP.
To better illustrate this point, let us imagine the extreme case:
P
<
, meaning
that infinite processors are available. In addition, if one considers that the multipro-
=
∞